내부 구성 요소가 실행되지 않는 이유

Question

그래서 VHDL로 계층 적 구성 요소를 만들었습니다. 현재 최상위 엔티티는 다음과 같습니다.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

--This component takes 2 numbers written in scientific notation and returns the same numbers with the same exponent 

entity exp_equalizer is 

    generic(
     TOTAL_BITS : natural := 23; 
     EXP_BITS : natural := 6 
    ); 

    port(
     man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0); 
     exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0); 
     man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0); 
     exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0); 
     man_1_out : out std_logic_vector((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto 0); --extended precision 
     man_2_out : out std_logic_vector((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto 0); 
     exp_out : out std_logic_vector(EXP_BITS - 1 downto 0); 
     difference : out unsigned(EXP_BITS - 1 downto 0) 
    ); 
end exp_equalizer; 

architecture exp_equalizer_arq of exp_equalizer is 

    signal exp_1   : std_logic_vector(EXP_BITS - 1 downto 0)    := (others => '0'); 
    signal exp_2   : std_logic_vector(EXP_BITS - 1 downto 0)    := (others => '0'); 
    signal man_1   : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0'); 
    signal man_2   : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '0'); 
    signal comparer_greater : std_logic           := '0'; 
    signal comparer_smaller : std_logic           := '1'; 
    signal smaller_exp  : std_logic_vector(EXP_BITS - 1 downto 0)    := (others => '0'); 
    signal greater_exp  : std_logic_vector(EXP_BITS - 1 downto 0)    := (others => '0'); 
    signal smaller_man  : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '1'); 
    signal greater_man  : std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0) := (others => '1'); 

    component comparer is 
     generic(
      BITS : natural := 16 
     ); 

     port(
      number1_in  : in std_logic_vector(BITS - 1 downto 0); 
      number2_in  : in std_logic_vector(BITS - 1 downto 0); 
      first_greater : out std_logic; 
      second_greater : out std_logic; 
      equals   : out std_logic 
     ); 

    end component; 

    component binary_multiplexer is 
     generic(
      BITS : natural := 16 
     ); 
     port(
      number1_in : in std_logic_vector(BITS - 1 downto 0); 
      number2_in : in std_logic_vector(BITS - 1 downto 0); 
      chooser : in std_logic; 
      mux_output : out std_logic_vector(BITS - 1 downto 0) 
     ); 
    end component; 

    for greater_exp_mux : binary_multiplexer use entity work.binary_multiplexer; 
    for smaller_exp_mux : binary_multiplexer use entity work.binary_multiplexer; 
    for greater_man_mux : binary_multiplexer use entity work.binary_multiplexer; 
    for smaller_man_mux : binary_multiplexer use entity work.binary_multiplexer; 
    for comparer_0 : comparer use entity work.comparer; 

begin 

    comparer_0 : comparer 
     generic map(BITS => EXP_BITS) 
     port map(
      first_greater => comparer_smaller, 
      second_greater => comparer_greater, 
      number1_in  => exp_1, 
      number2_in  => exp_2, 
      equals => open 
     ); 

    greater_exp_mux : binary_multiplexer 
     generic map(BITS => EXP_BITS) 
     port map(
      chooser => comparer_greater, 
      number1_in => exp_1, 
      number2_in => exp_2, 
      mux_output => greater_exp 
     ); 

    smaller_exp_mux : binary_multiplexer 
     generic map(BITS => EXP_BITS) 
     port map(
      chooser => comparer_smaller, 
      number1_in => exp_1, 
      number2_in => exp_2, 
      mux_output => smaller_exp 
     ); 

    greater_man_mux : binary_multiplexer 
     generic map(BITS => TOTAL_BITS - EXP_BITS - 1) 
     port map(
      chooser => comparer_greater, 
      number1_in => man_1, 
      number2_in => man_2, 
      mux_output => greater_man 
     ); 

    smaller_man_mux : binary_multiplexer 
     generic map(BITS => TOTAL_BITS - EXP_BITS - 1) 
     port map(
      chooser => comparer_smaller, 
      number1_in => man_1, 
      number2_in => man_2, 
      mux_output => smaller_man 
     ); 

    process(exp_1, exp_2, man_1, man_2, comparer_greater, comparer_smaller, smaller_exp, greater_exp, smaller_man, greater_man) is 
     variable shifting_difference : unsigned(EXP_BITS - 1 downto 0)        := (others => '0'); 
     variable extended_man_greater : std_logic_vector((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto 0) := (others => '0'); 
     variable extended_man_smaller : std_logic_vector((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto 0) := (others => '0'); 
    begin 
     exp_1 <= exp_1_in; 
     exp_2 <= exp_2_in; 
     extended_man_greater((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto (TOTAL_BITS - EXP_BITS - 1)) := greater_man; 
     extended_man_smaller((TOTAL_BITS - EXP_BITS - 1) * 2 - 1 downto (TOTAL_BITS - EXP_BITS - 1)) := smaller_man; 
     shifting_difference := unsigned(greater_exp) - unsigned(smaller_exp); 
     man_1_out <= std_logic_vector(shift_right(unsigned(extended_man_smaller), to_integer(shifting_difference))); 
     man_2_out <= extended_man_greater; 
     exp_out <= greater_exp; 
    end process; 

end architecture; 

그리고 난

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity exp_equalizer_tb is 
end entity; 

architecture exp_equalizer_tb_arq of exp_equalizer_tb is 

    signal man_1_in : std_logic_vector(15 downto 0) := (others => '0'); 
    signal exp_1_in : std_logic_vector(5 downto 0) := (others => '0'); 
    signal man_2_in : std_logic_vector(15 downto 0) := (others => '0'); 
    signal exp_2_in : std_logic_vector(5 downto 0) := (others => '0'); 
    signal man_1_out : std_logic_vector(31 downto 0) := (others => '0'); 
    signal man_2_out : std_logic_vector(31 downto 0) := (others => '0'); 
    signal exp_out : std_logic_vector(5 downto 0) := (others => '0'); 
    signal difference : unsigned(5 downto 0) := "000000"; 

    component exp_equalizer is 
     generic(
      TOTAL_BITS : natural := 23; 
      EXP_BITS : natural := 6 
     ); 

     port(
      man_1_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0); 
      exp_1_in : in std_logic_vector(EXP_BITS - 1 downto 0); 
      man_2_in : in std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0); 
      exp_2_in : in std_logic_vector(EXP_BITS - 1 downto 0); 
      man_1_out : out std_logic_vector((TOTAL_BITS - EXP_BITS - 2) * 2 + 1 downto 0); --extended precision 
      man_2_out : out std_logic_vector((TOTAL_BITS - EXP_BITS - 2) * 2 + 1 downto 0); 
      exp_out : out std_logic_vector(EXP_BITS - 1 downto 0); 
      difference : out unsigned(EXP_BITS - 1 downto 0) 
     ); 
    end component; 
    for exp_equalizer_0 : exp_equalizer use entity work.exp_equalizer; 

begin 

    exp_equalizer_0 : exp_equalizer 
     generic map(TOTAL_BITS => 23, EXP_BITS => 6) 
     port map(
      exp_1_in => exp_1_in, 
      exp_2_in => exp_2_in, 
      man_1_in => man_1_in, 
      man_2_in => man_2_in, 
      exp_out => exp_out, 
      man_1_out => man_1_out, 
      man_2_out => man_2_out, 
      difference => difference 
     ); 

    process 
     type pattern_type is record 
      m1 : std_logic_vector(15 downto 0); 
      e1 : std_logic_vector(5 downto 0); 
      m2 : std_logic_vector(15 downto 0); 
      e2 : std_logic_vector(5 downto 0); 
      mo1 : std_logic_vector(31 downto 0); 
      mo2 : std_logic_vector(31 downto 0); 
      eo : std_logic_vector(5 downto 0); 
     end record; 
     -- The patterns to apply. 
     type pattern_array is array (natural range <>) of pattern_type; 
     constant patterns : pattern_array := (
      ("0000000000000001", "000000", "0000000000000001", "000000", "00000000000000010000000000000000", "00000000000000010000000000000000", "000000"), 
      ("0000000000000001", "111110", "0000000000000000", "111111", "00000000000000010000000000000000", "00000000000000000000000000000000", "111111") 
     ); 

    begin 
     for i in patterns'range loop 
      -- Set the inputs. 
      exp_1_in <= patterns(i).e1; 
      exp_2_in <= patterns(i).e2; 
      man_1_in <= patterns(i).m1; 
      man_2_in <= patterns(i).m2; 

      wait for 100 ms; 

      assert patterns(i).mo1 = man_1_out report "BAD MANTISSA 1, GOT: " & integer'image(to_integer(signed(man_1_out))); 
      assert patterns(i).mo2 = man_2_out report "BAD MANTISSA 2, GOT: " & integer'image(to_integer(signed(man_2_out))); 
      assert patterns(i).eo = exp_out report "BAD EXP, GOT: " & integer'image(to_integer(signed(exp_out))); 
      -- Check the outputs. 
     end loop; 
     assert false report "end of test" severity note; 
     wait; 
    end process; 
end; 

는하지만 난 볼 수 있어요 무엇을, 내부 구성 요소 (비교 자 및 멀티플렉서) "실행"되지 않는 및 결과 포트는이 테스트 벤치를 사용하여 테스트입니다 결코 바뀌지 않았다.

모든 구성 요소에는 프로세스의 트리거로 모든 IN 포트가 있습니다.

저는 이것에 대해 조금 읽었으며 구성 요소가 프로세스 내에서 실행될 수 없다는 것을 알았습니다. 어쩌면 내가 할 때 어쩌면 : exp_1 < = exp_1_in; exp_2 < = exp_2_in; 실제로 구성 요소가 실행되지 않습니다.

그러나 여기에서 시도한 것과 매우 유사한 예를 보았습니다. https://www.altera.com/support/support-resources/design-examples/design-software/vhdl/v_hier.html

내 문제가 어디 있는지 알 수 없습니다. 모든 구성 요소를 개별적으로 테스트했으며 모두 작동합니다.

편집 :

내가 그런 GHDL -e exp_equalizer_tb 그리고 마지막으로, 내가 실행 를 실행하고 함께 테스트 벤치에서 실행 파일을 구축 -a GHDL와 모든 파일을 분석하고있다 ./ exp_equalizer

프로젝트의 모든 구성 요소에 대해 동일한 작업을 수행하는 스크립트를 만들었으며 모든 프로젝트에 어설 션 및 보고서를 사용하여 테스트 벤치를 만들었고 모두 작동합니다 벌금. 예상되는 결과를 얻지 못하는이 구성 요소에 있습니다.

Answer 1

다른 엔티티의 소스 코드가 없으면 특정 문제를 재현 할 수 없습니다. 특히, 내가 과거에 구성으로 많은 문제를 본 적이

for greater_exp_mux : binary_multiplexer use entity work.binary_multiplexer; 
for smaller_exp_mux : binary_multiplexer use entity work.binary_multiplexer; 
for greater_man_mux : binary_multiplexer use entity work.binary_multiplexer; 
for smaller_man_mux : binary_multiplexer use entity work.binary_multiplexer; 
for comparer_0 : comparer use entity work.comparer; 

:

내가 GHDL를 사용하지 않는

하지만 내가 문제가이 라인이 될 수 있다고 여기 추측을 던질거야 신디사이저와. 일반적으로 시뮬레이터에서는 문제가되지 않지만 누가 알 수 있습니다.

플러스, 귀하의 경우에는 어쨌든 그들은 목적이 없어 보일 것입니다. 따라서 IMO는 물론 그들을 내버려 두어야합니다.