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systemc의 쓰레드에 대해 읽는 동안 함수 내에서 while(true) 루프를 사용해야한다고합니다. 왜 그래야만하지?시스템 C의 쓰레드 및 클럭 스레드
1 //-----------------------------------------------------
2 // This is my second Systemc Example
3 // Design Name : first_counter
4 // File Name : first_counter.cpp
5 // Function : This is a 4 bit up-counter with
6 // Synchronous active high reset and
7 // with active high enable signal
8 //-----------------------------------------------------
9 #include "systemc.h"
10
11 SC_MODULE (first_counter) {
12 sc_in_clk clock ; // Clock input of the design
13 sc_in<bool> reset ; // active high, synchronous Reset input
14 sc_in<bool> enable; // Active high enable signal for counter
15 sc_out<sc_uint<4> > counter_out; // 4 bit vector output of the counter
16
17 //------------Local Variables Here---------------------
18 sc_uint<4> count;
19
20 //------------Code Starts Here-------------------------
21 // Below function implements actual counter logic
22 void incr_count() {
23 // For threads, we need to have while true loop
24 while (true) {
25 // Wait for the event in sensitivity list to occure
26 // In this example - positive edge of clock
27 wait();
28 if (reset.read() == 1) {
29 count = 0;
30 counter_out.write(count);
31 // If enable is active, then we increment the counter
32 } else if (enable.read() == 1) {
33 count = count + 1;
34 counter_out.write(count);
35 }
36 }
37 } // End of function incr_count
38
39 // Below functions prints value of count when ever it changes
40 void print_count() {
41 while (true) {
42 wait();
43 cout<<"@" << sc_time_stamp() <<
44 " :: Counter Value "<<counter_out.read()<<endl;
45 }
46 }
47
48 // Constructor for the counter
49 // Since this counter is a positive edge trigged one,
50 // We trigger the below block with respect to positive
51 // edge of the clock
52 SC_CTOR(first_counter) {
53 // Edge sensitive to clock
54 SC_THREAD(incr_count);
55 sensitive << clock.pos();
56 // Level Sensitive to change in counter output
57 SC_THREAD(print_count);
58 sensitive << counter_out;
59 } // End of Constructor
60
61 }; // End of Module counter